32 bit binary up counter with byte multiplexed three-state outputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 lsi pin assignment - top view scan enable scan reset/load test count b7 out b6 out b5 out b4 out v dd (+v) alt count b3 out b2 out b1 out b0 out reset cascade en out v ss (-v) figure 1 LS7060C count features: ? dc to 50mhz count frequency ? byte multiplexer ? dc to 10mhz byte output scan frequency ? +4.75v to +5.25v operation (v dd - v ss ) ? three-state data outputs; bus, ttl and cmos compatible ? inputs ttl and cmos compatible ? unique cascade feature allows multiplexing of successive bytes of data in sequence in multiple counter systems ? low power dissipation ? LS7060C (dip), LS7060C-s (soic) - see figure 1 ? ls7061c (dip), ls7061c-s (soic) - see figure 2 description: the LS7060C/ls7061c are cmos silicon gate, 32 bit up counters. the ics include latches, multiplexer, byte output se- quencer, eight three-state binary data output drivers and output cascading logic. description of operation: 32 bit binary up counter - LS7060C (ls7061c) the 32 bit static ripple through counter increments on the neg- ative edge of the input count pulse. maximum ripple time is 20ns transition count of 32 ones to 32 zeros. guaranteed count frequency is dc to 50mhz. see figure 9a (9b) for block diagram. count, alt count (LS7060C) input count pulses to the 32 bit counter may be applied through either of these two inputs. the alt count input circuitry con- tains a schmitt trigger network which allows proper counting with "infinitely" long clock edges. a high applied to either of these two inputs inhibits counting. count (ls7061c) input count pulses to the 32 bit counter may be applied through this input. this input is the most significant bit of the external data byte. reset all 32 counter bits are reset to zero when reset is brought low for a minimum of 20ns. reset must be high for a minimum of 10ns before next valid count can be recorded. test count count pulses may be applied to the last 16 bits of the binary counter through this input, as long as bit 16 of the counter is a low. the counter advances on the negative transition of these pulses. this input is intended to be used for test purposes. note : LS7060C and ls7061c can directly replace ls7060 and ls7061 in all existing applications. january 2002 7060c/61c-012102-1 lsi/csi lsi computer systems, inc. 1235 walt whitman road, melville, ny 11747 (631) 271-0400 fax (631) 271-0405 LS7060C ls7061c u l a3800 latches 32 bits of latch are provided for storage of counter data for the LS7060C. 40 bits of latch are provided for the ls7061c of which eight are for storage of a high speed external prescaling counter and the remaining 32 are for the contents of the chip counter data. all latches are loaded when the load input is brought low for a minimum of 10ns and kept low until a minimum of 20ns has elapsed from previous negative edge of count pulse (ripple time). storage of valid data occurs when load is brought high for a minimum of 20ns before next negative edge of count pulse or reset. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 b4 out b5 out b0 in b1 in b2 in b7 out b3 in test count scan reset/load scan enable b6 out v dd (+v) (count) b7 in b3 out b6 in b2 out b5 in b1 out b4 in b0 out reset cascade enable out vss (-v) pin assignment - top view figure 2 lsi ls7061c advance information
scan counter and decoder the scan counter is reset to the least significant byte position (state 1) when scan reset input is brought low for a mini- mum of 10ns. the scan counter is enabled for counting as long as the enable input is held low. the counter advances to the next significant byte position on each negative transition of the scan pulse. when the scan counter advances to state 5 for the LS7060C or stage 6 for the ls7061c it disables the output drivers and stops in that state until scan reset is again brought low. scan when the scan counter is enabled, each negative transition of this input advances the scan counter to its next state. when scan is low the data outputs are disabled. when scan is brought high the data outputs are enabled and present the latched counter data corresponding to the present state of the scan counter. therefore, in microprocessor applications, the data output bus may be utilized for other activities while new data is propagating to the outputs. this positive scan pulse can be viewed as a "place the next byte on my bus" instruction from the microprocessor. minimum positive and negative pulse widths of 10ns for the scan signal are required for scan counter operation. scan reset/load when this input is brought low for a minimum of 10ns, the scan counter is reset to state 1, the least significant byte position, and the latches are simultaneously loaded with new count information. enable when this input is high, the scan counter and the data outputs are disabled. when enable is low, the scan counter and data outputs are enabled for normal operation. transition of this input should only be made while the scan input is in a low state in order to pre- vent false clocking of the scan counter. cascade enable this output is normally high. it transitions low and stays low when the scan counter advances to state 5 for LS7060C and state 6 for ls7061c. in a multiple counter system this output is connected to the enable input of the next counter in the cascade string. the scan input and scan reset/load input are carried to all the counters in the "cascade". counter 1 then presents its bytes of data to the output bus on each positive transition of the scan pulse as previously discussed. when state 5 for LS7060C or state 6 for ls7061c of counter 1 is achieved, counter 2 presents its data to the output bus. this sequence continues until all counters in the cascade have been addressed. see figure 5 for an illustration of a 3 device cascade design. this output is ttl and cmos compatible. three-state data output drivers the eight data output drivers are disabled when either enable input is high, the scan counter is in state 5 for LS7060C and state 6 for ls7061c, or the scan input is low. the output drivers are ttl and bus compatible. absolute maximum ratings: parameter symbol value unit storagetemperature t stg -55 to +150 ? operating temperature t a 0 to +70 ? voltage (any pin to v ss ) v in +10 to -0.3 v dc electrical characteristics: (v dd = +5v ?5%, v ss = 0v, t a = 0?c to +70?c unless otherwise noted.) parameter symbol min max unit conditions quiescent power supply i dd - 0.5 ma v dd = max, outputs no load, current frequency power supply current i dd 4 - ma 15 mhz operating frequency v dd = max, outputs no load power supply current i dd - 8 ma at maximum operating frequency v dd = max, outputs no load input high voltage v ih +3.5 v dd v - input low voltage v il 0 +0.6 v - output high voltage cascade enable v oh +2.4 - v i o = -6ma, v dd = min b0 - b7 v oh +2.4 - v i o = -33ma, v dd = min output low voltage cascade enable v ol - +0.4 v i o = 3ma, v dd = min b0 - b7 v ol - +0.4 v i o = 10ma, v dd = min output source current isource -34 - ma v o = +1.2v, v dd = min b0 - b7 outputs -36 - ma v o = +0.8v, v dd = min -38 - ma v o = +0.4v, v dd = min output sink current isink 25 - ma v o = +1.2v, v dd = min b0 - b7 outputs 20 - ma v o = +0.8v, v dd = min 10 - ma v o = +0.4v, v dd = min output leakage current i ol - 10 na v o = +.4v to +2.4v, v dd = min b0 - b7 (off state) input capacitance c in - 6 pf t a = 25?c, f = 1mhz output capacitance c out - 12 pf t a = 25?c, f = 1mhz input leakage current i li - 10 na v dd = max enable, reset, scan 7060c/61c-012102-2
dynamic electrical characteristics: (v dd = +5v ?5%, v ss = 0 v , t a = 0?c to +70?c unless otherwise noted.) parameter symbol min max unit conditions count frequency fc dc 50 mhz - (all count inputs) count pulse width t cpw 10 - ns measured at 50% point, (all count inputs) max tr, t f = 1ns count ripple time t cr - 20 ns transition from 32 ones to 32 zeros from negative edge of count pulse reset pulse width t rpw 20 - ns measured at 50% point (all counter stages max t r , t f = 10ns fully reset) reset removal time t rr - 10 ns measured from reset signal at v ih (reset removed from all counter stages) scan frequency f sc - 10 mhz scan pulse width t scpw 50 - ns measured at 50% point max t r , t f = 10ns scan reset/load t rscpw 10 - ns measured at 50% point pulse width max t r , t f = 5ns (all latches loaded and scan counter reset to least significant byte) scan reset/load t rscr - 10 ns measured from removal time scan reset/load at v ih (reset removed from scan counter; load command removed from latches) output disable t dod - 5 ns transition to output high delay time impedance state measured (b0 - b7) from scan at v il or enable at v ih output enable t doe - 5 ns transition to valid on state delay time measured from scan at v ih (b0 - b7) and enable at v il ; delay to valid data levels for c ol = 10pf and one ttl load or valid data currents for high capacitance loads output delay time t dce - 10 ns negative transition from scan at v il cascade enable and st5 of scan counter or positive transition from scan reset/load at v il to valid data levels for c ol = 12pf and one ttl load symbol min max unit conditions input current *scan reset/load i ih - -3.5 ? v dd = max, v ih = +3.5v i il - -5 ? v dd = max, v il = 0v **all count inputs i ih - 5 ? v dd = max, v ih = +3.5v i il - 1 ? v dd = max, v il = 0.35v *input has internal pull-up resistor to v dd ** inputs have internal pull-down resistor to v ss 7060c/61c-121901-3
valid valid valid valid lsb lsb+1 t dce t doe lsb +2 msb t dod figure 3a. scan counter & decoder outputs timing diagram for LS7060C t dce t rscpw t rscr t scpw t scpw scan reset enable scan st1 (int.) st2 (int.) st3 (int.) st4 (int.) st5 (int.) enable (int.) cascade enable data outputs valid valid valid valid lsb lsb+1 t dce t doe lsb +2 lsb+3 t dod figure 3b. scan counter & decoder outputs timing diagram for ls7061c. t dce t rscpw t rscr t scpw t scpw scan reset enable scan st1 (int.) st2 (int.) st3 (int.) st4 (int.) st5 (int.) enable (int.) cascade enable data outputs st6 (int.) valid msb 7060c/62c-121801-4
figure 4. counter timing diagram reset count load t rpw t rr + t cpw t rscpw t rscr t cr t cpw t rpw t cpw t rr+tcpw a en sc reset sc ce b en sc reset sc ce c en sc reset sc ce output data bus enable scan reset scan figure 5. illustration of a 3 device cascade end of scan 7060c/61c-121901-5 scan reset enable scan cascade enable a cascade enable b cascade enable c data byte on bus package a 1 2 3 4 5 1 2 3 4 5 b 1 2 3 4 5 c figure 6. timing diagram for the 3 device cascade (end of scan)
pr d c q q s r to count input inhibit count pulses (same as input to alt count) count pulses (same as input to alt count) inhibit to count input figure 7. synchronizing inhibit with count pulses method 2 method 1 7060c/61c-121801-6 radiation pulse detector voltage discriminators prescalers scan processor en ce en ce en ce b u s cascade enable ls7061c pulse voltage proportional to energy of radiation figure 8. application example: high speed differential energy analyzer note : the processor subtracts counts from successive counters to determine the differential energy spectrum the information included herein is believed to be accurate and reliable. however, lsi computer systems, inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use.
8 bit binary counter r c load 8 bit latch g mux gate 8 bit binary counter r c load 8 bit latch g mux gate 8 bit binary counter r c load 8 bit latch g mux gate 8 bit binary counter r c load 8 bit latch g mux gate test count 5 state static scan counter and decoder (stops in state 5 until scan reset causes reset to state one) st1 st2 st3 st4 c sc r sc v dd v ss enable scan scan reset/load 8 bit mux bus en three state output drivers 8 bits enable lsb msb data out st5 cascade enable reset figure 9a. LS7060C block diagram alt count count b0 b0 b7 +v -v 18 9 11 10 12 1 2 13 7 6 5 4 3 17 16 15 14 b0 b7 b0 b7 b0 b7 8 b1 b2 b3 b4 b5 b6 b7 8 bit binary counter r c load 8 bit latch g mux gate 8 bit binary counter r c load 8 bit latch g mux gate 8 bit binary counter r c load 8 bit latch g mux gate 8 bit binary counter r c load 8 bit latch g mux gate test count 6 state static scan counter and decoder (stops in state 6 until scan reset causes reset to state one) st2 st3 st4 st5 c sc r sc v dd v ss enable scan scan reset/load 8 bit mux bus en three state output drivers 8 bits enable lsb msb data out st6 cascade enable reset figure 9b. ls7061c block diagram b0 b0 b7 +v -v 1 12 14 13 15 16 10 9 7 5 3 24 23 20 18 b0 b7 b0 b7 b0 b7 11 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 load 8 bit latch g mux gate data in (count) st1 22 19 2 21 17 6 8 4
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